As the global semiconductor industry confronts the physical limits of traditional transistor miniaturization, Chinese tech giant Huawei has proposed a new framework that shifts the focus from geometric shrinkage to time efficiency.

He Tingbo, a senior executive at Huawei, introduced the Tau (τ) Scaling Law​ during a keynote speech at the 2026 IEEE International Symposium on Circuits and Systems (ISCAS) on Monday. 

The proposal comes amid widespread concerns that Moore's Law, the industry's guiding principle for over five decades, is facing diminishing economic returns and technical bottlenecks.

Unlike conventional approaches that prioritize reducing transistor size, the τ Scaling Law emphasizes compressing signal propagation delay across the entire computing stack.

To implement this principle, Huawei has developed a multi-level co-optimization mechanism spanning devices, circuits, chips, and systems. Key innovations include LogicFolding, an architecture designed to break traditional physical boundaries to shorten critical-path wiring and UnifiedBus, a protocol aimed at reducing system-level communication latency.

Industry observers note that such systemic optimization is crucial for the industry, especially as advanced process nodes become increasingly difficult and expensive to achieve.

According to He, the company has designed and mass-produced 381 chips​ using this methodology over the past six years, spanning sectors from consumer electronics to artificial intelligence infrastructure.

A significant milestone is scheduled for the fourth quarter of 2026, with the release of a new Kirin chip series​ featuring the LogicFolding architecture.

Looking further ahead, Huawei projects that its high-end chips could reach transistor densities equivalent to 1.4-nanometer-class processes by 2031.

Despite the competitive landscape of global chip technology, He emphasized the importance of global cooperation. "The semiconductor industry thrives on openness and collaboration," He noted, adding that no single company can independently solve the challenges of the industry's evolution.

The presentation drew considerable attention from researchers and industry executives, reflecting growing interest in alternative approaches to semiconductor scaling beyond traditional transistor miniaturization.