From geometry to time: Decoding Huawei's Tau (τ) Scaling Law

At the 2026 IEEE International Symposium on Circuits and Systems (ISCAS), He Tingbo, a senior executive at Huawei, outlined the Tau (τ) Scaling Law, a framework proposing that the industry shift its primary optimization target from transistor size to signal speed.

What is the Tau Scaling Law?

In circuit theory, the Greek letter tau​ (τ) represents a time constant: roughly, how quickly a signal can swing from one state to another without getting bogged down by resistance and capacitance in the wiring and the device itself (often discussed as RC delay). The smaller τ is, the faster and more efficiently a circuit can toggle and process data.

To visualize this, imagine a vast factory assembly line. For decades, Moore's Law focused on making the workers (transistors) smaller to pack more onto the floor. The Tau Scaling Law argues that beyond shrinking workers, the industry must redesign the layout to shorten the distance products travel.

To achieve this, Huawei has developed LogicFolding, a technology designed to break traditional two-dimensional layout boundaries. By restructuring logic to shorten critical wiring paths, the company aims to boost transistor density and performance without relying exclusively on the most advanced lithography nodes.

The urgency of a new coordinate system

The proposal arrives as Moore's Law faces diminishing economic returns. As transistor shrinkage becomes increasingly costly, the semiconductor industry is searching for a new performance framework – and perhaps a new narrative – for the post-Moore era.

One reason is that performance bottlenecks are increasingly shifting away from transistor density alone. RC delay and interconnect bottlenecks have been central concerns in chip design for decades, particularly as Moore's Law slows. Technologies such as chiplets, advanced packaging and 3D stacking already reflect a broader industry transition toward system-level optimization, where data movement efficiency is becoming as important as transistor density itself.

Tian Feng, director of Kuaisi Manxiang Research Institute, described Huawei's proposal as a strategic pivot. "Huawei has redefined the yardstick of performance evolution, shifting the goal from transistor size to signal delay," Tian said. "This changes the game from a single track of process chasing to a dual track of process plus system innovation."

Tian argued that the industry is hitting a dual constraint: physical scaling is slowing while the cost of each successive advance continues to rise, making "measuring progress by nanometers" an increasingly incomplete metric. He described the timing of Huawei's τ framework as an attempt to offer a system-level alternative coordinate while the industry still lacks a widely accepted post-Moore framework.

Tian further framed LogicFolding as a response to those constraints: if traditional transistor scaling is increasingly constrained by lithography costs and manufacturing complexity, the remaining optimization frontier lies at the system level – through shorter critical paths, tighter interconnects and 3D-style proximity.

According to Xinhua, Hu Yanping, a professor at the Digital Frontier Research Institute at Shanghai University of Finance and Economics, said the semiconductor industry is approaching an AI-driven inflection point. "Explosive computing demand requires someone to send the turn signal," Hu said. "It is encouraging that companies are beginning to move beyond path dependency and explore new paradigms, even if the ultimate test will remain real-world validation."

What might it mean for the industry?

Huawei noted tangible progress, reporting that it has designed and mass-produced 381 chips​ based on this methodology over the past six years. The company projects that its high-end chips could reach transistor densities equivalent to 1.4-nanometer-class processes by 2031.

Analysts suggest the feasibility hinges on execution rather than just theory. 

Zhang Lixing, chairman of Wuxi Chipown Micro, offered a simplified analogy: "Moore's Law is like putting more workers on a production line. The Tau Law is about speeding up the turnover of parts on that line."

Zhang explained that the value lies in system integration. "It optimizes data transmission efficiency across the stack," he said. "Advanced packaging is a means to this end, but the core metric is the reduction of signal transfer time."

However, experts caution that scaling this approach requires overcoming significant bottlenecks. 

Cang Wei, vice president of Xpeedic Technology, pointed to system-level EDA tools​ as the critical enabler. "The Tau Law provides one ruler for process engineers, architects, and system designers to collaborate," Cang said. "But for this to benefit the entire industry, we must strengthen domestic capabilities in system-level EDA to support this new paradigm."

Looking ahead, He Tingbo framed the Tau Scaling Law as a collective endeavor rather than a proprietary solution. "No single company can independently find all the answers," she noted, calling for closer collaboration among scientists, engineers and industry peers worldwide to ensure the sustainable development of the electronics industry.

Related: Huawei unveils 'Tau Scaling Law​' to hit 1.4-nanometer equivalent chip density by 2031