Huawei's rotating chairman Xu Zhijun said chipmakers can achieve cutting-edge performance using mature 7-nanometer-class process technology by adopting the company's "He's Law" design methodology, dramatically cutting costs compared with chasing the latest fabrication nodes, according to interviews published on Sunday.

"If companies follow He's Law, they can make chips based on 7nm technology at lower cost, why wouldn't they?" Xu said in an interview with Chinese chip tech outlet Jiwei.

The methodology, also known as the "τ-law" or "Tau Scaling Law," was first presented at the IEEE International Symposium on Circuits and Systems (ISCAS) recently by He Tingbo, Huawei's semiconductor business president.

Xu stressed it is not meant to replace Moore's Law – the decades-old observation that transistor density doubles roughly every two years – but is a practice-tested approach Huawei developed to focus on reducing the time constant (τ) across device, circuit, chip and system levels rather than relying solely on transistor shrinking.

"When Gordon Moore proposed his law, he didn't convince everyone to follow him either," Xu told another outlet SemiInsights. "If He's Law truly has vitality, it will develop naturally without persuasion. We are simply providing a path we have already verified." Huawei confirmed the authenticity of both interviews to CGTN.

The technique's most distinctive element is "logic folding," in which multiple dies – the individual chips cut from a silicon wafer – are designed as a single integrated unit from the start, enabling better critical-path optimization. Xu distinguished it from conventional 3D stacking with a simple analogy: "Folding means folding a single sheet of paper; stacking means putting two separate sheets on top of each other."

The economics are central to the pitch. Xu noted that skyrocketing costs at advanced nodes make traditional scaling increasingly unsustainable. Logic folding on mature nodes offers a dramatically cheaper alternative.

Huawei's HiSilicon unit will demonstrate the technique commercially later this year with the Kirin 2026 chip, the first mobile processor to apply logic folding. Huawei expects the design to achieve the equivalent of 1.4nm-class transistor density by 2031.